New method of growing high-quality graphene promising for next-gen technology

Researchers at UC Santa Barbara have discovered a method to synthesize high quality graphene in a controlled manner that may pave the way for next-generation electronics application.

The discovery by UCSB researchers turns graphene production into an industry-friendly process by improving the quality and uniformity of graphene using efficient and reproducible methods. They were able to control the number of graphene layers produced – from mono-layer to bi-layer graphene – an important distinction for future applications in electronics and other technology.

"Intel has a keen interest in graphene due to many possibilities it holds for the next generation of energy- efficient computing, but there are many roadblocks along the way," added Intel Fellow, Shekhar Borkar. "The scalable synthesis technique developed by Professor Banerjee's group at UCSB is an important step forward."

Journal Carbon - Synthesis of high-quality monolayer and bilayer graphene on copper using chemical vapor deposition

Foresight 2011 - Mesoporous Sensors: From Explosives to Cancer

Mesoporous Sensors: From Explosives to Cancer
Robert Meagley, PhD, CEO/CTO of ONE-Nanotechnologies LLC

One-nanotechnologies website - We create faster, more accurate, and more cost-effective tools for biomarker analysis, making more efficient and precise human health diagnostics possible. Our patent-pending technology measures proteins and other disease and cancer biomarkers through the use of precisely printed photonic nanodevices.

Early disease detection uses biochemical processes to find biomarkers. These biochemicals add complexity, variability and error to the results. Specificity and simplicity are better! Our technology provides both specificity and simplicity without use of antibodies. Our chips are optimized for the detection of particular breast cancer, colorectal cancer, lung cancer and ovarian cancer, as well as heart disease biomarkers. These five diseases are responsible for the majority of non-accident death in Europe and North America.

Extending our thin films technology into the realm of chemical threat detection, our approach has been shown to be an effective discrimination system for biochemical and energetic materials. Nerve agent surrogates and RDX have been identified as trace constituents in air and water. Electronic discrimination of chemical and biochemical threats addresses key issues in environmental health and safety as well as food security and military applications.

* fault tolerant systems
* using plasma processing to spray thin coatings
* plasma cleaning
* vacuum plasma spray
* 350 watts plasma enhanced CVD (chemical vapor deposition)

* embedded sensor technology for chemical detection and food safety
* lower cost systems

Growth of Titanium Dioxide Nanorods in 3D-Confined Spaces

Nanoletters - Growth of Titanium Dioxide Nanorods in 3D-Confined Spaces

Three-dimensional (3D) nanowire (NW) networks are promising architectures for effectively translating the extraordinary properties of one-dimensional objects into a 3D space. However, to uniformly grow NWs in a 3D confined space is a serious challenge due to the coupling between crystal growth and precursor concentration that is often dictated by the mass flow characteristic of vapor or liquid phase reactants within the high-aspect ratio submicrometer channels in current strategies. We report a pulsed chemical vapor deposition (CVD) process that successfully addressed this issue and grew TiO2 nanorods uniformly covering the entire inner surface of highly confined nanochannels. We propose a mechanism for the anisotropic growth of anatase TiO2 based on the surface-reaction-limited CVD process. This strategy would lead to the realization of NW-based 3D nanoarchitectures from various functional materials for the applications of sensors, solar cells, catalysts, energy storage systems, and so forth.

Large-Diameter Graphene Nanotubes Synthesized Using Ni Nanowire Templates

Nanoletters - Large-Diameter Graphene Nanotubes Synthesized Using Ni Nanowire Templates

We report a method to synthesize tubular graphene structures by chemical vapor deposition (CVD) on Ni nanowire templates, using ethylene as a precursor at growth temperature of around 750 °C. Unlike carbon nanotubes that are synthesized via conventional routes, the number of graphene layers is determined by the growth time and is independent of the tube diameter and tube length, which follow those of the nanowire template. This allows us to realize large-diameter tubes with shells comprising a few or many layers of graphene as desired. Thin graphene layers are observed to be highly crystalline, and of uniform thickness throughout the length of the nanowire. Raman analysis shows the presence of a small level of defects typical of CVD-grown graphene. The metallic core could be removed by chemical etching to result in a collapsed tube. Backgated field-effect transistor measurements were conducted on the collapsed graphene tube. This approach to the realization of tubular graphene offers new opportunities for graphene-based nanodevices.

Fabrication and electrical integration of robust carbon nanotube micropillars by self-directed elastocapillary densification

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Vertically-aligned carbon nanotube (CNT) "forest" microstructures fabricated by chemical vapor deposition (CVD) using patterned catalyst films typically have a low CNT density per unit area. As a result, CNT forests have poor bulk properties and are too fragile for integration with microfabrication processing. We introduce a new self-directed capillary densification method where a liquid is controllably condensed onto and evaporated from CNT forests. Compared to prior approaches, where the substrate with CNTs is immersed in a liquid, our condensation approach gives significantly more uniform structures and enables precise control of the CNT packing density and pillar cross-sectional shape. We present a set of design rules and parametric studies of CNT micropillar densification by this method, and show that self-directed capillary densification enhances the Young's modulus and electrical conductivity of CNT micropillars by more than three orders of magnitude. We calculate that densification increases the Young’s Modulus of the micropillars from 1.56 MPa to 2.24 GPa. The reduction in cross-sectional area is 17, the modulus increases by a factor of more than 1400. The great increase in the modulus can be attributed to the change in collective loading mechanism of individual tubes within the forest which is caused by the reduction in CNT-CNT spacingOwing to the outstanding properties of CNTs, this scalable process will be useful for the integration of CNTs as functional material in microfabricated devices for mechanical, electrical, thermal, and biomedical applications.
33 page pdf from Arxiv

Role of Kinetic Factors in Chemical Vapor Deposition Synthesis of Uniform Large Area Graphene Using Copper Catalyst

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This is research towards make large area graphene using copper catalyst with chemical vapor deposition

In this article, the role of kinetics, in particular, the pressure of the reaction chamber in the chemical vapor deposition (CVD) synthesis of graphene using low carbon solid solubility catalysts (Cu), on both the large area thickness uniformity and the defect density are presented. Although the thermodynamics of the synthesis system remains the same, based on whether the process is performed at atmospheric pressure (AP), low pressure (LP) (0.1−1 Torr) or under ultrahigh vacuum (UHV) conditions, the kinetics of the growth phenomenon are different, leading to a variation in the uniformity of the resulting graphene growth over large areas (wafer scale). The kinetic models for APCVD and LPCVD are discussed, thereby providing insight for understanding the differences between APCVD vs LPCVD/UHVCVD graphene syntheses. Interestingly, graphene syntheses using a Cu catalyst in APCVD processes at higher methane concentrations revealed that the growth is not self-limiting, which is in contrast to previous observations for the LPCVD case. Additionally, nanoribbons and nanostrips with widths ranging from 20 to 100 nm were also observed on the APCVD grown graphene. Interactions between graphene nanofeatures (edges, folds) and the contaminant metal nanoparticles from the Cu etchant were observed, suggesting that these samples could potentially be employed to investigate the chemical reactivity of single molecules, DNA, and nanoparticles with monolayer graphene.

Applied Materials Claims Game Changing Flowable Chemical Vapor Deposition for 256 Gigabyte 3D NAND Flash Chips at 20 Nanometer Lithography

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Applied Materials, Inc. today announced its breakthrough Applied Producer(R) Eterna(TM) FCVD(TM) (Flowable CVD(1)) system, the first and only film deposition technology capable of electrically isolating the densely-packed transistors in 20nm-and-below memory and logic chip designs with a high-quality dielectric film. The system will enable NAND skyscraper (3d NAND memory) wafers with 256 gigabyte NAND flash chips. It will also enable the creation of complex finfet transistors which are needed for faster and lower power chips. It will also enable DRaM 4F2 8 gigabit DDR4.

The gaps between these transistors can have aspect ratios of more than 30:1 -- five times higher than current requirements -- and highly-complex profiles. The Eterna FCVD system's unique process completely fills these gaps from the bottom up, delivering a dense, carbon-free dielectric film at up to half the cost of spin-on deposition methods -- which require more equipment and many additional process steps.

"The need to fill smaller and deeper structures in advanced chip designs creates a physical roadblock for existing deposition technologies. Applied has broken through this barrier today with the introduction of its new Eterna FCVD system -- delivering the disruptive technology that can enable the continued progress of Moore's Law," said Bill McClintock, vice president and general manager of Applied's DSM/ CMP(2) Business Unit. "With the Eterna FCVD system, Applied continues its decade-long leadership in gap-fill technology, providing a unique, simplified and cost-effective solution for customers to meet the challenges of multiple new chip generations."

Applied's proprietary Eterna FCVD process delivers a liquid-like film that flows freely into virtually any structure shape to provide a bottom up, void-free fill. The Eterna FCVD system is installed at six customer sites for DRAM, Flash and Logic applications, where it is integrated on Applied's benchmark Producer platform.

Applied Materials has a page on their new technology.

* It allow for planarized cap
* They can create 100 angstrom (10 nanometer) thick film without defects

Single-Layer Graphene Nearly 100% Covering an Entire Substrate

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Arxiv - Single-Layer Graphene has covered nearly 100% of an entire substrate (13 pages)

Graphene has recently attracted a great deal of interest in both academia and industry because of its unique electronic and optical properties as well as its chemical, thermal, and mechanical properties. The superb characteristics of graphene make this material one of the most promising candidates for various applications, such as ultrafast electronic circuits and photodetectors, clean and renewable energy and rapid single-molecule DNA sequencing. The electronic properties of the graphene system rely heavily on the number of graphene layers and effects on the coupling with the underlying substrate. Graphene can be produced by mechanical exfoliation of graphite, solution approaches thermal decomposition of SiC, and chemical vapor deposition/segregation on catalytic metals. Despite significant progress in graphene synthesis, production with fine control over the thickness of the film remains a considerable challenge. Here, we report on the synthesis of nearly 100% coverage of single-layer graphene on a Ni(111) surface with carbon atoms diffused from a highly orientated pyrolytic graphite (HOPG) substrate. Our results demonstrate how fine control of thickness and structure can be achieved by optimization of equilibrium processes of carbon diffusion from HOPG, segregation from Ni, and carbon diffusion at a Ni surface. Our method represents a significant step toward the scalable synthesis of graphene films with high structural qualities and finely controlled thicknesses and toward realizing the unique properties of graphene.

Fujitsu Labs Can Form Graphene Transistors on Silicon Wafers

Physorg reports that Fujitsu Laboratories has developed a novel technology for forming graphene transistors directly on the entire surface of large-scale insulating substrates at low temperatures while employing chemical-vapor deposition (CVD) techniques which are in widespread use in semiconductor manufacturing.

Fujitsu Laboratories developed novel technology that allows for graphene to be formed on insulating film substrate via CVD at the low fabrication-temperature of 650°C, enabling graphene-based transistors to be directly formed on the entire surface of substrates. Although the test substrate employed was a 75-mm silicon substrate (wafer) with oxide film, the new technique is applicable to larger 300-mm wafers as well.

1. Low-temperature synthesis of multi-layer graphene featuring thickness controlled via CVD, on entire surface of substrate


2. Process for forming transfer-free graphene transistors






Fujitsu Laboratories also developed a process for forming transistors that use graphene as the channel material, as outlined in the picture. This process is independent of wafer size, so it can be applied to large-scale substrates.

1. First, an iron catalyst is formed into the desired channel shape, using a conventional photolithographic process.

2. Graphene is then formed on the iron layer via CVD.

3. Source and drain electrodes of titanium-gold film are formed at both ends of the graphene, thereby "fixing" the graphene.

4. Next, just the iron catalyst is removed using acid, leaving the graphene suspended between the source and drain electrodes, with the graphene "bridged" between the electrodes.

5. Using atomic-layer deposition (ALD), a method for forming thin films, a layer of hafnium dioxide (HfO2) is grown on top of the graphene to stabilize the graphene.

6. Finally, a gate electrode is formed on top of the graphene and through the HfO2, resulting in the formation of a graphene transistor.

Lithographic Graphitic Memories

HPC Wire reports that advances by the Rice University lab of James Tour have brought graphite’s potential as a mass data storage medium a step closer to reality and created the potential for reprogrammable gate arrays that could bring about a revolution in integrated circuit logic design. (H/T Sander Olson)

In a paper published in the online journal ACS Nano, Tour and postdoctoral associate Alexander Sinitskii show how they've used industry-standard lithographic techniques to deposit 10-nanometer stripes of amorphous graphite, the carbon-based, semiconducting material commonly found in pencils, onto silicon. This facilitates the creation of potentially very dense, very stable nonvolatile memory for all kinds of digital devices.

With backing from a major manufacturer of memory chips, Tour and his team have pushed the technology forward in several ways since a paper that appeared last November first described two-terminal graphitic memory. While noting advances in other molecular computing techniques that involve nanotubes or quantum dots, he said none of those have yet proved practical in terms of fabrication.

Not so with this simple-to-deposit graphite. "We're using chemical vapor deposition and lithography -- techniques the industry understands," said Tour, Rice's Chao Professor of Chemistry and a professor of mechanical engineering and materials science and of computer science. "That makes this a good alternative to our previous carbon-coated nanocable devices, which perform well but are very difficult to manufacture."

James Tour of Rice university has developed easily accessible memory devices based upon stripes of chemical vapor deposited (CVD) nanosized irregular discs of graphitic material that can be layered in stripes ≤10 nm thick with controllable lengths and widths. These lithographic graphitic stripes, which can be easily fabricated in large quantities in parallel by conventional fabrication techniques (such as CVD and photo- or e-beam lithography), with yields >95%, are shown to exhibit voltage-induced switching behavior, which can be used for two-terminal memories. These memories are stable, rewritable, and nonvolatile with ON/OFF ratios up to 10^7, switching times down to 1 μs (tested limit), and switching voltages down to 3−4 V. The major functional parameters of these lithographic memories are shown to be scalable with the devices’ dimensions.

Graphite's other advantages were detailed in Tour's earlier work: the ability to operate with as little as three volts, an astoundingly high on/off ratio (the amount of juice a circuit holds when it’s on, as opposed to off) and the need for only two terminals instead of three, which eliminates a lot of circuitry. It's also impervious to a wide temperature range and radiation; this makes it suitable for deployment in space and for military uses where exposure to temperature extremes and radiation is a concern.

Tour's graphite-forming technique is well-suited for other applications in the semiconductor industry. One result of the previous paper is a partnership between the Tour group and NuPGA (for "new programmable gate arrays"), a California company formed around the research to create a new breed of reprogrammable gate arrays that could make the design of all kinds of computer chips easier and cheaper.

Currently, antifuse FPGAs can be programmed once. But this graphite approach could allow for the creation of FPGAs that can be reprogrammed at will. Or-Bach said graphite-based FPGAs would start out as blanks, with the graphite elements split. Programmers could "heal" the antifuses at will by applying a voltage, and split them with an even higher voltage.

Such a device would be mighty handy to computer-chip designers, who now spend many millions to create the photolithography mask sets used in chip fabrication. If the design fails, it's back to square one.

Carbon-based memory architectures promise to revolutionize FPGA design, according to the founder of a chip startup.

Startup NuPGA was founded by Zvi Or-Bach, a winner of the EE Times Innovator of the Year Award. He previously founded eASIC and Chip Express. Or-Bach has applied for a patent, along with Rice University, for its carbon-based memory process developed by professor James Tour. The approach uses graphite as the reprogrammable memory element inside vias on otherwise conventional FPGAs.

"Using graphite in the vias as fuse is a very interesting concept," said Dean Freeman, senior analyst at Gartner Inc. "We are going to see a lot of very innovative, creative thinking along these lines in the next five years."

Rice University researchers developed a bulk chemical process that converted nanotubes into nanoribbons, providing the raw material needed to perfect a technique based on using voltage pulses to make or break connections--essentially turning the carbon ribbons into reprogrammable switches. NuPGA plans to harness these reprogrammable switches in FPGAs by inserting graphite into vias between chip layers, allowing them to be reconfigured on-the-fly.

"Graphene can become interesting when it is shaved down to below 10-nanometer widths into ribbon structures, making it much easier to modulate at low voltages," said Tour. "Graphene won't be ready to go head-to-head with Intel until 2015, when lithography dips below that 10-nanometer size. By that time, much of the market could already be using thin films of carbon materials for bulk electronics in places where silicon can't be used today."

By making thin films from his slurries of carbon nanotubes--what he calls "graphene nanoribbons"--Tour perfected the memory architecture to be used in reprogrammable switches in NuPGA's chips. The process allows a voltage pulse to reprogram FPGAs by making or breaking the connection pathway through graphite-filled vias.