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August 08, 2013

Applied Materials roadmap to 3 nanometers through precise control of materials for FinFET scaling

Applied Materials Adam Brand made a presentation at 2013 Semicon West which laid out a roadmap to get to 3 nanometer lithography.

Precision Materials to Meet Scaling Challenges Beyond 14nm (18 pages)

Beyond 14nm, as we move to 10 and 7nm, a new fin material will be required — probably silicon-germanium (SiGe), or perhaps just pure germanium.

SiGe will take us to 7nm then a new transistor structure is needed at 5 nanometers.

FinFET created a larger surface area, mitigating the effects of quantum tunneling, both Gate All Around (GAA) FETs and vertical tunneling FETs (TFETs), would again allow for shorter gates and lower voltages

A Gate All Around essentially consists of nanowire source and drains, surrounded by a gate. A vertical TFET is similar in that it uses nanowires, but the actual method of operation is very different from conventional FETs

Precise control of materials is needed to deliver the required structure.

FinFET scaling requires precision control of materials
* CMP: precision through in-situ process control
* Dielectrics: composition tuning
* Junction: optimized activation
* Metal gate: multi Vt by metal gate composition and implant
* Metal gate: improved materials to control resistance at scaled CD
* Contact: optimized surface doping with implant + laser anneal









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