Jack Sun, chief technologist at TSMC, said quad patterning--four passes through a lithography stepper using four different masks--was one of several options TSMC is exploring as it works on path finding for the process.
Earlier, Intel said it has found a way to make 10-nm chips using quad patterning that is still cost effective. It aims to start production of chips in the process in as little as two years.
Sun showed the same near-term roadmap for TSMC the company showed at its own event earlier this month. It includes starting limited test production of 20-nm planar chips by the end of the year and a 16-nm FinFET process starting test production late next year.
Sun said the new 20-nm process holds traditional advances of as much as 35 percent in performance and power capabilities. New transistor structures like FinFETs will provide an even greater boost, he said.
As for 10-nm, TSMC “is in serious path finding development of it,” he said. “In the next five years, we can see down to 5 nm easily, but of course there are some path finding challenges yet to come,” he added.
Sun also reported TSMC has successfully made prototypes of both FPGAs and graphics processors using its Chip on Wafer on Substrate (CoWoS) process. The technique, also known as 2.5-D packaging, links multiple die laid side-by-side on a common substrate.
He also noted SMC reported in June progress making through silicon vias as small as 50 microns, about half the size of previous interconnects.
TSMC and partners in total spent an estimated $11,9 billion on their chip design and manufacturing ecosystem, Sun said. “That’s bigger than any single company, and its open--it is one of the biggest innovation forces” in the industry, he said.
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