The 10 nm process would debut in 2015 or later. It would require quadruple patterning for some mask layers but “it’s still economical,” said Mark Bohr, director of Intel’s technology and manufacturing group.
Intel is considering many options including ones not on this slide Bohr showed.
Bohr is not revealing any details of either Intel’s 14 or 10 nm process plans yet. His comments focused only on technical feasibility.
The company has long worked on extreme ultraviolet (EUV) lithography and recently agreed to invest $4.1 billion in ASML to drive it forward. “EUV is very important to us, and that’s we we invested in ASML, but we have multiple paths that we pursue such as immersion with multiple patterning,” Bohr said
Intel expects to use at least double patterning in some layers of some chips at 14 nm. If immersion is used at 10 nm, more layers will require double patterning and some will even require quadruple patterning, he said.
At 14 nm, Bohr said, "the increased wafer costs [associated with double patterning] is still being offset by improved density, so our cost per transistor continues to go down with each generation on a very steady trend,” he said
That trend would continue, he suggested, even if immersion is used at 10 nm. As of today, “EUV is later than I would like, and I can’t count on it for sure,” he said.
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