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August 17, 2012

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

Nature Scientific Reports - Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.


Microphotographs of (a) printed OTFTs and (b) via connections. (c) Schematic of an OTFT cross-section.



Printed electronic components provide mechanical flexibility and stretchability as well as low-cost manufacturability, complementing the computing power of silicon electronics.

Two key elements that can enable complex printed circuits are logic and memory. Organic semiconductors are particularly suitable for printed logic because they can be processed in solution. Recently, organic thin-film transistors (OTFTs) with performance comparable to that of inorganic amorphous silicon TFTs have been reported. Organic circuits have been fabricated using photolithographic processes which offer high reliability but are incompatible with high-throughput, low-cost manufacturing methods, such as roll-to-roll processing. Fundamental circuit building blocks, such as inverters and differential pairs as well as a non-rewritable RFID tag have been demonstrated in a printed process, representing first steps towards more complex circuits.

Combining logic and rewritable memory can enhance the capability of printed electronics. The inclusion of memory allows identification or history information to be maintained. Non-volatile ferroelectric memory in passive and active matrix arrays has been demonstrated. The addition of addressing logic is necessary for these arrays to be scalable: a binary logic decoder allows 2N rows in an array to be controlled with just N-bits. The provides a scalable addressing scheme for matrix arrays common in electronics and is widely applicable to arrayed sensor and display applications.

In this work, we use additive fabrication processes that are entirely compatible with roll-to-roll print manufacturing to demonstrate small-scale complex circuits. An inkjet-patterned 3-bit memory decoder is realized for addressing ferroelectric memory capacitors. The all-additive process includes both n- and p-type organic semiconductors, enabling the utilization of complementary logic to reduce power consumption and improve circuit stability. We describe our device models and use of simulation-based design, essential for complex circuits. We explain the key challenges in fabrication of complex printed circuits and elucidate the minimum performance requirements of materials and devices for reliable digital logic. Finally, we present the results of combining the decoder with ferroelectric capacitors, to demonstrate a scalable memory array with integrated logic.

A flexible electronic system with organic memory and logic circuits is achieved by additive printing, and this is designed with tolerance to the device variations and instability found in print manufacturing. The decoder described here enables the scalability of printed memory, which is essential to future applications with sensor networks, smart tags and packaging, and numerous other applications. Moreover, the decoder circuit is applicable to addressing other types of arrays often used in large-area electronic applications. The circuit design techniques and device performance guidelines here are generally applicable to other organic circuits. These methodologies will enable design toolkits, ultimately leading towards the realization of manufacturable printed electronics.

Fabrication process

Circuits are fabricated on a mechanically flexible substrate cut from 125-μm polyethylene naphthalate (PEN) film (Dupont Teijin). Electrode contacts are fabricated by inkjet-printing a silver-nanoparticle solution (Cabot). The source/drain electrodes for p-channel transistors are treated with tetrafluoro-tetracyanoquinodimethane (F4TCNQ, 0.5% by weight in dichlorobenzene) to reduce contact resistance. There is no contact treatment for the n-channel transistors. Channel lengths of 35 μm are used in the circuit design.


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