Stanford University researchers led by professors Subhasish Mitra and H.-S. Philip Wong have produced a series of breakthroughs that represent the most advanced computing and storage elements yet created using carbon nanotubes.
These high-quality, robust nanotube circuits are immune to the stubborn and crippling material flaws that have stumped researchers for over a decade, a difficult hurdle that has prevented the wider adoption of nanotube circuits in industry. The advance represents a major milestone toward what researchers call "very-large scale integrated systems" based on nanotubes.
"The first carbon nanotubes wowed the research community with their exceptional electrical, thermal and mechanical properties over a decade ago, but this recent work at Stanford has provided the first glimpse of their viability to complement silicon CMOS transistors," said Larry Pileggi, professor of electrical and computer engineering at Carnegie Mellon University.
An electron microscope image showing carbon nanotube transistors (carbon nanotubes) arranged in an integrated logic circuit.
CREDIT: Courtesy Stanford University
IEEE - Carbon Nanotube Robust Digital VLSI
ABSTRACT - Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.
At least two major barriers remain before carbon nanotubes can be harnessed into technologies of practical impact. First, processing must achieve near-perfect alignment of nanotubes. Misaligned nanotubes introduce detrimental, stray, conducting paths and faulty functionality into the circuits. Second, engineers must eliminate metallic carbon nanotubes (as opposed to more desirable semiconducting carbon nanotubes) from the circuits. Metallic carbon nanotubes lead to short circuits, excessive power leakage and susceptibility to circuit noise. No carbon nanotube synthesis technique has yet produced exclusively semiconducting nanotubes.
Realizing that better processes alone will never overcome these imperfections, the Stanford engineers circumvented the barriers using a unique imperfection-immune design. They have produced the first full-wafer-scale digital logic structures based on carbon nanotubes that are unaffected by misaligned and mis-positioned nanotubes. Additionally, they have addressed the challenges of metallic carbon nanotubes with the invention of a technique to remove these undesirable elements from their circuits.
"Carbon nanotube transistors are attractive for many reasons as a basis for dense, energy efficient integrated circuits in the future," said Supratik Guha, director of the Physical Sciences Department at the IBM Thomas J. Watson Research Center. "But, being borne out of chemistry, they come with unique challenges as we try to adapt them into microelectronics for the first time. Chief among them is variability in their placement and their electrical properties. The Stanford work, which looks at designing circuits that take into consideration such variability, is therefore an extremely important step in the right direction."
The Stanford design approach has two striking features in that it sacrifices virtually none of carbon nanotubes’ energy efficiency and also is compatible with existing fabrication methods and infrastructure, pushing the technology a significant step toward to commercialization.
"This is very interesting and creative work. While there are many difficult challenges ahead, the work of Wong and Mitra makes good progress at solving some of these challenges," said Bokor.
"This transformative research is made all the more promising by the fact that it can co-exist with today’s mainstream silicon technologies, and leverage today’s manufacturing and system design infrastructure, providing the critical feature of economic viability," said Betsy Weitzman of the Focus Center Research Program at the Semiconductor Research Corporation.
The engineers next demonstrated the possibilities of their techniques by creating the essential components of digital integrated systems: Arithmetic circuits and sequential storage, as well as the first monolithic 3D integrated circuits with extreme levels of integration.
"Many researchers assumed that the way to live with imperfections in carbon nanotube manufacturing was through expensive fault-tolerance techniques. Through clever insights, Mitra and Wong have shown otherwise. Their inexpensive and practical methods can significantly improve carbon nanotube circuit robustness, and go a long way toward making carbon nanotube circuits viable," said Sachin S. Sapatnekar, editor-in-chief of the journal. "I anticipate high reader interest in the paper."
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