In an effort to sustain the advance of these devices while curbing power consumption, diverse research communities are looking for hybrid or alternative technologies. Nanoelectromechanical (NEM) switch technology is one option that shows great promise.
“NEM switches consist of a nanostructure (such as a carbon nanotube or nanowire) that deflects mechanically under electrostatic forces to make or break contact with an electrode,” said Horacio Espinosa, James N. and Nancy J. Farley Professor in Manufacturing and Entrepreneurship at the McCormick School of Engineering at Northwestern University.
NEM switches, which can be designed to function like a silicon transistor, could be used either in standalone or hybrid NEM-silicon devices. They offer both ultra-low power consumption and a strong tolerance of high temperatures and radiation exposure.
Given their potential, the past decade has seen significant attention to the development of both hybrid and standalone NEM devices.
Nature Nanotechnology - Nanoelectromechanical contact switches
Nanoelectromechanical (NEM) switches are similar to conventional semiconductor switches in that they can be used as relays, transistors, logic devices and sensors. However, the operating principles of NEM switches and semiconductor switches are fundamentally different. These differences give NEM switches an advantage over semiconductor switches in some applications — for example, NEM switches perform much better in extreme environments — but semiconductor switches benefit from a much superior manufacturing infrastructure. Here we review the potential of NEM-switch technologies to complement or selectively replace conventional complementary metal-oxide semiconductor technology, and identify the challenges involved in the large-scale manufacture of a representative set of NEM-based devices.
Basic operating characteristics of NEM switches
One longstanding challenge has been to create arrays of millions of the nanostructures, such as carbon nanotubes, that are used to make these NEM devices. (For perspective, modern silicon electronics can have billions of transistors on a single chip.) The researchers’ review describes the methods demonstrated to date to create these arrays, and how they may provide a path to realizing hybrid NEM-CMOS devices on a mass scale.
Similarly, while individual NEM devices show extremely high performance, it has proven difficult so far to make them operate reliably for millions of cycles, which is necessary if they are to be used in consumer electronics. The review details the various modes of failure and describes promising methods for overcoming them.
An example of the advances that facilitate improved robustness of NEM switch technologies is reported in the current issue of Advanced Materials. Here Espinosa and his group show how novel material selection can greatly improve the robustness of both hybrid NEM-CMOS and standalone NEM devices.
“NEM devices with commonly-used metal electrodes often fail by one of a variety of failure modes after only a few actuation cycles,” said Owen Loh, a PhD student at Northwestern University and co-author of the paper, currently at Intel.
Simply by replacing the metal electrodes with electrodes made from conductive diamond-like carbon films, the group was able to dramatically improve the number of cycles these devices endure. Switches that originally failed after fewer than 10 cycles now operated for 1 million cycles without failure. This facile yet effective advance may provide a key step toward realizing the NEM devices whose potential is outlined in the recent review.
Hybrid NEM–CMOS devices.
The properties of two hybrid NEM–CMOS devices — dynamic OR gates and SRAMs — are summarized in the table below. Individual hybrid NEM–CMOS devices can also be combined to create more complex systems. For example, individual SRAM cells (either hybrid or purely NEM-based) can be combined with CMOS decoders to form look-up tables or SRAM-based field-programmable arrays. There have also been proposals to build hybrid SRAM devices in which carbon nanotubes are used as the active elements of the NEM switches and also as the channel of the transistor
Outlook for NEMS
Through the past decade, the outstanding performance achieved in small numbers of NEM switches has earned these devices a place in the ITRS roadmap as potential successors or hybrid complements to conventional CMOS. Although the next decade will see a continued focus on demonstrating new types of functionality in NEM-based devices, greater emphasis will be placed on scaling and integration. Important challenges include improving reliability and developing methods that are able to create well-ordered arrays of nanostructures. It is encouraging to note that many of the other challenges associated with the manufacture of NEM-based devices have already been conquered by the current semiconductor industry.
As it is not possible to construct large-scale arrays of NEM switches at present, it is also not possible to perform the parametric studies that are needed to fully optimize device designs (for example, to identify the best geometries and materials to balance the competing effects of mechanical compliance, contact resistance and so on) in a statistically significant manner. Analytical and computational models that can predict the highly dynamic and inherently multi-physics response of devices (in which the electrical, mechanical and thermal responses are all coupled to each other) will therefore become increasingly important. And as devices continue to scale down, these models will need to include quantum effects such as the Casimir effect (which can, for example, influence the gap at which pull-in occurs). Modelling is also needed to improve the yield from various nanomanufacturing techniques.
The first applications of NEM-based switches are likely to be in niche areas, such as ultralow power or high-temperature systems, where scalability and speed are less critical. The introduction of fully integrated electromechanical computing architectures will involve overcoming the challenges associated with NEM–CMOS integration, such as matching operating voltages and packaging concerns. As manufacturing methods and device architectures continue to evolve, NEM-switch performance will begin to approach that predicted in models. Once this has been achieved, NEM–static-random-access-memory (SRAM) architectures and other hybrid systems may rival conventional CMOS devices in terms of switching speeds while offering reduced power consumption. Finally, as NEM switches are pushed to compete more directly with CMOS transistors in performance, the adoption of the single-nanostructure architectures will potentially facilitate the highest levels of performance, although this will also involve overcoming enormous scientific and technological challenges.
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