The SRC-guided research significantly extends the path for cores to communicate by reading and writing to a shared space – known as cache-coherent shared memory. In each core, one or more caches hold the subset of memory locations that most recently have been written and read by the core.
Cache coherence protocols are built into hardware in order to guarantee that each cache and memory controller can access shared data at high performance. As computational demands on the cores increase, so do concerns that the protocol will be slow or energy-inefficient when there are multiple cores.
“We have refuted calls for a radical design change by showing that, using already existing techniques, we can create cache coherence protocols that scale to hundreds and perhaps even thousands of cores,” said Sorin.
“Our results allow us to confidently predict that, with these new protocols, on-chip coherence is here to stay. Computer systems don’t need to abandon current compatibilities to accommodate even hundreds of cores,” Sorin added. “Chip area and energy consumption may limit future multi-core chips, but our research refutes conventional wisdom that multi-core scalability of the memory system would be the primary scaling bottleneck.”
This news means that not only will the computer industry be able to avoid radically changing the programming paradigm from the mainstream technique of cache-coherent shared memory, but the solution developed by Sorin and his colleagues also facilitates backward compatibility with the vast amount of legacy code written for cache-coherent shared memory. Thus, as the industry plans for the future, it gains a path for scalability without requiring all new software.
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