April 06, 2012

Integration, Architecture, and Applications of 3D CMOS Memristor Circuits

Integration, Architecture, and Applications of 3D CMOS Memristor Circuits (67 pages)

Professor Tim Cheng adn Dimitri Strukov at the University of California at Santa Barbara described how 3-D techniques could realize the dream of semiconductor memristors.

Using a hybrid 3-D integration technique, Cheng's memory structure sandwiched the memristive material between the perpendicular lines of a crossbar at the astronomical density of 100,000 gigabits-per-square-centimeter with 1 billion gigabits-per-second bandwidth.

The biggest challenge of the design was to overcome the mismatch between the fine-grain dimension of the crossbar-based devices and the interface pins of the chip, which Cheng overcame with novel 3-D vias that were tilted with respect to the interface pins.

If Successful, 3D Hybrids Can Achieve…..
• Unprecedented memory density
– Footprint of a nano‐device is 4F nano 2/K, for K vertically integrated crossbar layers
– Potentially up to 10^14 (100 trillion) bits on a single 1‐cm2 chip
• Enormous memory bandwidth
– Potentially up to 10^18 (1 quintillion or 1 million trillion) bits/second/cm2
• At manageable power dissipation
• With abundant redundancy for yield/reliability

ACM paper - 3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications

In this paper, we give an overview of our recent research efforts on monolithic 3D integration of CMOS and memristive nanodevices. These hybrid circuits combine a CMOS subsystem with several layers of nanowire crossbars, consisting of arrays of two-terminal memristors, all connected by an area-distributed interface between the CMOS subsystem and the crossbars. This approach combines the advantages of CMOS technology, including its high flexibility, functionality and yield, with the extremely high density of nanowires, nanodevices and interface vias. As a result, the 3D hybrids can overcome limitations pertinent to other 3D integration techniques (such as through-silicon vias) and enable 3D circuits with unprecedented memory density (up to 10^14 bits on a single 1-cm2 chip) and aggregate interlayer communication bandwidth (up to 10^18 bits per second per cm2) at manageable power dissipation. Such performance represents a significant step towards addressing the most pressing needs of modern compact electronic systems.

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