Pages

April 25, 2012

DARPA and partners look to accelerate development beyond CMOS and highly complex systems that are more than the sum of parts

The Focus Center Research Program ("FCRP"), a consortium of industrial participants and the Defense Advanced Research Projects Agency ("DARPA"), (the "Consortium")solicits white papers from U.S. universities for collaborative, multidisciplinary, multi-university research in selected areas of principal interest.

The goal of this collaborative effort between the Department of Defense and the industrial participants is to increase substantially the unprecedented multi-decade record of uninterrupted performance improvement in information processing power and storage capacity of integrated circuits and related systems.

They want to improve faster than Moore's law.

The Consortium seeks to address emerging challenges in semiconductor and systems technologies by concentrating resources on high-risk, high-payoff, long-range innovative research to accelerate the productivity growth and performance enhancement of semiconductor integrated circuits and multi-scale systems.

The Consortium seeks proposals addressing one or more of the following seven focus technology areas which are organized into two major thrusts:

NEXT: Highly Complex Systems

Technology Areas for NEXT - The mission of the NEXT thrust area is to enable highly complex systems with capabilities well beyond those available today, i.e., to augment beyond the "sum of the parts."





1. High performance analog devices for high speed wireless, THz electronics for imaging, sensing, novel power devices: New analog and mixed signal circuit architectures and techniques are needed that enable the efficient transmission (generation), reception (sensing), manipulation
and processing of analog signals (information) as well as conversion of analog signals to the digital domain.

2. Vehicle and Distributed Sensor Networks: Designs and implementation of integrated modular architecture (IMA) communication networks (i.e. distributed systems) are needed, including methodology and tools to support the choice of synchronous/asynchronous communication systems and the co-design of functionality and implementation platforms.

3. Computing System Architectures based on CMOS technology: Research is needed on highly parallel computing including data and interconnection architecture for nonconventional computing systems based on CMOS.

4. Tools and methods for design, verification, and predictive modeling, including physical modeling: Research is needed that explores and develops the tools that will enable realization of new systems, components, and technologies that will be developed in the 10 year timeframe.

Detailed pamphlet for proposers (22 pages)

Analog circuit/architecture examples include (but are not limited to):

• Dynamically field programmable (adaptive, scalable) RF multifunction components/arrays
• High efficiency, wideband, linear low noise and power amplifiers (with dynamic RF power control)
• High power mm-wave sources
• Self-healing/self-calibrating RF circuits
• Cognitive sensors (radios)
• High dynamic range, energy efficient, millimeter wave direct sampling (RF to bits)
• RF photonics
• Biometrics (including standoff biometrics detection)
• On-chip adaptive/tunable, high Q filters
• On-chip power conditioning circuits
• On-chip thermal management
• On-chip oscillators for high fidelity frequency sources


3 – Explore Computing System Architectures based on CMOS Technology

Scope: Highly parallel computing including data and interconnection architecture, nonconventional computing systems based on CMOS.

The goal of this research implies highly parallel and efficient systems including computing, interconnect and storage architecture, with the ability in the architecture to cover a range of implementations in size and energy proportional performance by a factor of 100x or larger in the same generation. In addition, this goal implies architectures that will enable systems whose performance will scale throughout time for at least one decade, delivering 30x or more performance at a constant size and power consumption at the end of the decade.

Background: Considering that projections of existing CMOS-based components are not expected to be able to continuing to deliver on the desired metrics, new architectures must be capable to effectively integrate emerging CMOS-based capabilities such as 3D silicon, novel memory devices, reconfigurable logic, heterogeneity, etc., in addition to already established principles such as massive parallelism, workload optimized systems, extreme energy efficiency, and reliability. These elements must be combined in scalable and efficient manner, including the enablement techniques required for successful and lasting exploitation as well as evolution from current system architectures. The exploration should include system modeling tools, system architecture, system software, middleware, application software, programming models, software development tools, circuits, devices, hardware design and verification tools.

Research Needs: Explore computing system architectures based on CMOS technology that allow continued performance and efficiency improvements in line with historic growth, namely doubling device density every two years, in the presence of diminishing or even stalling benefits arising from technology scaling, addressing workloads end-to-end. Such exploration shall target new computational and physical architectures that will bridge the gap between ultimately scaled CMOS and a beyond-CMOS approach until this non-CMOS technology becomes widespread, This beyond-CMOS or non-CMOS technology might need to break away from the pure von-Neumann model so that it or they can incorporate new mechanisms that are more scalable and efficient than traditional ones, while at the same time continue to support and evolve the software practices that are prevalent and emerging. The efforts shall address continued evolution in efficiency and scalability of existing systems architectures, as well as non-conventional architectures that introduce novel computing structures and programming models, all based on CMOS technology. The exploration should include the integration of these complementary approaches into an unified and adaptable system architecture. The resulting architectures must address improvements in: single-thread performance for Amdhal's law effects; scalability for parallel workloads and code regions; programming models for effective exploitation of the new architectures; energy proportional performance; reliability and security. The research efforts shall also address system modeling tools as well as methodologies and techniques to ensure the evolution of current systems to the new architectures. The research shall focus on architectures that are amenable for multiple generations of systems, covering the entire period up to the emergence of beyond-CMOS technologies and systems.


4) Other heterogeneous systems should be explored to exploit the full potential of not only driving new power devices but also integration of power and sensors, with their distinct thermal management requirements, enabling additional applications for the future.

Explore and develop the tools that will enable realization of the new systems, components, and technologies that will be developed in the 10 year timeframe. The timeframe for introduction of these systems into the market would be between 2020 and 2025.

Background: This program element addresses the need for energy efficient multi-scale systems, 3-D chips and architectures, multi-dimensional transistors, nanotubes and nanotechnology with 1-D and 2-D transport mechanisms. Optimizing these systems for energy, performance, density and cost are key to their success in the market. Verification and test of these extremely complex systems will be critical to their deployment. Architectural design and construction will require new models and paradigms to be developed that optimize multi-scale and multi-dimensional systems with completely new materials and components. None of the existing tools enable us to model or verify such systems today.

ACCEL: Semiconductor Technologies beyond CMOS

Technology Areas for ACCEL - The mission of the ACCEL thrust area is to identify and accelerate progress for new mainstream technologies beyond digital CMOS

1. Nonconventional material systems: Research is needed for improved and novel materials that enable three basic technologies: analog, memory and logic devices.

2. Quantum engineered devices and new sensors and transducers: Next generation technologies based on exploiting quantum level physics to provide capabilities well beyond state-of-the-art. Efforts should accelerate the integration of new material systems and quantum phenomena as the basis for the era beyond CMOS based devices. Preference will be given to ideas that have a clear path towards stable use in applications, e.g., at room temperature and with minimal shielding. Research is needed to identify new devices and sensors that can move the integrated circuit for computation and analog processing into the era of Beyond CMOS circuits.

3. Integrated circuits and computing architectures based on novel devices including both digital and analog: This research topic is chartered to find a new energy efficient architecture to replace the Von Neumann Computer Architecture and to optimize the overall performance and energy usage by optimally partitioning the computational system between signal processing in the analog domain at an I/O interface, and computation in the digital domain.

The research is expected to start in January 2013. There will be a checkpoint at 2.5 years to allow for re-direction as needed within the Centers; this will not be a re-competition. Overall program funding may reach a level of $40M per annum, depending on research progress and availability of funds.


1 – Nonconventional material systems

Scope: Improved and novel materials that enable 3 basic technologies: analog, memory and logic devices. These materials should address both new devices and applications as well as enhance existing device performance and provide new functionality.

Background: Over the past two decades introduction of new and improved materials to Si ICs has contributed prominently to the successful scaling of circuit density and performance. Two classes of materials illustrate this point. The first is introduction of Cu – Low k interconnect technology at the 180 nm technology node. The second is introduction of high k/metal gate technology at the 45nm node. New materials certainly will impact analog, logic, and memory applications as discussed in Research Needs below. New materials may introduce useful new functions (e.g., spin transfer torque)

Research Needs: In the analog arena new materials are needed for resistors, high voltage and high temperature electronics, capacitors, inductors, energy generation, and on-chip high density energy storage. The following materials currently being developed need better fundamental understanding and better growth processes to be integrated in commercial devices:

1) Epitaxial GaN, SiC, and diamond and associated integration materials such as dielectrics (e.g. AlN) and electrode materials for high voltage applications.
2) Complex metals and metal oxides for resistors with good temperature coefficient of resistance (TCR) e.g. CrSiCNO, CoAlO, and TiCrAlO
3) High-k capacitor materials – e.g. PLZT, ZrO, HfO, STO, AlOx, Ta2O5, Nb2O5 and electrodes and processes to integrate them into the back-end-of-line (BEOL)
4) Thin Film Batteries – Li based, or other
5) Organic materials for chemical sensing
6) Substrates for wide-bandgap semiconductor-based devices (e.g. diamond) for high temperature electronics

In the memory arena there is a need for materials enabling denser and more robust embedded non-volatile memories for the next decade and beyond. Some of the materials currently under consideration are:

1) Complex binary metal oxides for ReRAM, that can also enable multi state memory. These materials while seemingly common are not well understood for ReRAM applications. Some examples are: SiOx, HfOx, TiOx, etc.

2) Ferroelectric materials with high-k, polarization, etc:
a. Atomic layer epitaxy (ALE) of thin sub 20 nm complex metal oxides including ferroelectric (FE) materials. Some examples are ALE of SrRuO3 for MIM electrodes, and ALE of PbZrTiO3 for both planar and 3-D MIM stacks.
b. Perhaps new FE materials to replace PZT

2 – Quantum engineered devices and new sensors and transducers

Scope: Next generation technologies based on exploiting quantum level physics to provide capabilities well beyond state-of-the-art. Efforts should accelerate the integration of new material systems and quantum phenomena as the basis for the era beyond CMOS based devices. Preference will be given to ideas that have a clear path towards stable use in applications, e.g., at room temperature and with minimal shielding.

Background: As the CMOS scaling underlying the current era of improving computing performance can no longer provide the necessary reductions in power, there is a need for alternative energy efficient options for the next generation of microsystems. Quantum engineering of new physical phenomena, including many-body states and strongly coupled collective behaviors, offer promising opportunities for meeting these needs.

Research Needed
Summary of research needed to realize advanced devices based on quantum engineered effects
The MOSFET’s dependence on a charge barrier to control the “off” leakage current, requires every electron to cross the nkT energy barrier. However if a robust state variable with improved transport properties were available there is the possibility of reducing the energy required to control the barrier by orders of magnitude. Examples of quantum engineered states include, but are not limited to, anomalous quantum Hall states, transduction through opto-electro-mechanical states, topologically insulating states, 1-dimensional and 2-dimensional transport, and a variety of spintronic and magnetic states. Preferred approaches will architect the most energy efficient logic gate based on alternative state variables, while allowing scaling into the sub-10 nm spatial dimensions, and will include work on a compatible interconnect.

Beyond transistors there are a broad range of devices where combinations of nonconventional materials and quantum engineering offer the potential for significant innovation. These should target providing novel capabilities and improving performance over existing state-of-the-art by at least 1000X. Examples include utilizing spintronics to achieve improved energy times delay products compared to electron charge based switches, excitonic states for efficient transport, unique mixing of static electric and magnetic fields in collective states of topological insulators, and the protected spin and/or electronic transport with minimal back scattering made possible by engineering strong spin-orbit coupling. These physical phenomena and others offer the potential of novel control between magnetic and electric fields, high throughput interconnects, and unique combinations of low-power and high-speed devices.

Scope: Research in sensors and transducers is needed to identify technologies that can accelerate integration of new materials into CMOS integrated circuits and to identify new devices and sensors that move integrated circuits for computation and analog signal processing into the era of Beyond CMOS.

Background: Interfacing electronics with the “real world” involves sensors and transducers, the development of which has been a historical driver of integrated-circuit technology. This synergy should continue into the future as it becomes possible to sense and control the IC environment in new ways. In some cases, it will be efficient to integrate new sensors and transducers directly, adding new types of functionality to system-on-chip circuits and improving performance and efficiency of the overall system.

3 – Integrated circuits and computing architectures

Scope: This research topic is chartered to find a new energy efficient architecture to replace the Von Neumann Computer Architecture and to understand how to optimize the overall performance and energy by optimally partitioning the computational system between signal processing in the analog domain at an I/O interface, and computation in the digital domain. Hybrid analog and digital computation is envisaged to be applied to increase computation performance and efficiency (general purpose or application-specific with adaptation and learning) by exploring software, architecture, algorithms, circuits and beyond-CMOS devices and interconnect.

Background: Today’s computer architecture has not changed significantly for over sixty years since the Von Neumann architecture was developed. While it has been an extremely successful and versatile architecture and has undergone many changes in terms of its micro-architecture, it will face increased performance challenges in terms power efficiency (operations/joule) as well as power flux (W/cm-squared) and power density (W/cm-cubed) due to approaching scaling limitations with the fundamental underlying CMOS nano-technology.

However there are application specific computational algorithms and computer architectures emerging that have started to address improved efficiency for important and widely applicable applications such as pattern recognition, adaptable signal processing and machine learning. Application specific architectures have been found to be most energy efficient, and together with adaptability and reconfigure-ability, they can be applied across a large field of computational tasks while tolerating errors. Two examples of these are the machine learning algorithms that use Associative Memory and Bayesian Networks.

The input and output functions of a computing system are analog due to the nature of signals that they need to handle. Computers need to process data from numerous sensor networks, recognize events, and drive a variety of peripherals accordingly. In order to decrease the power dissipation of the system, it is of advantage to treat these signals in the analog domain and to postpone digitizing them. Thus there is a need to develop novel analog signal processing techniques/algorithms. Architectures like cellular neural networks need to be further developed to cover such tasks.

There is also an increasing amount of understanding developing about the architectural principles of biological function and this has created an emerging area of application specific computational techniques that use hybrid analog and digital circuits. Such circuits are built with similar design principles as electrical and chemical operation of neurons. By using high redundancy of operation and normally OFF operation, these circuits could be made robust to electronic noise and unreliable electronic components while remaining highly energy efficient.

Research Needs: Hybrid analog and digital computation is envisaged to be applied to increase computation performance and efficiency (general purpose or application-specific with adaptation and learning) by exploring software, architecture, algorithms, circuits and beyond-CMOS devices—interconnects. Examples include, but are not limited to:

1. Hybrid analog and digital techniques that are bio- or cell- inspired to lower the energy of certain application specific computations.
2. Hybrid analog/digital systems where the analog/digital ratio has been optimized consistent with the application requirements
3. Stochastic techniques that incorporate or exploit variability in devices.
4. Machine learning algorithms such a Bayesian Networks that use associative memories and the probabilistic nature of the data.
5. Efficient spatial temporal data flow in massively parallel architectures such as Cellular Nonlinear Network (CNN) systolic arrays for pattern recognition.
6. New computational elements; examples include, but not limited to, coupled oscillator arrays for pattern detection and associated memory architectures.
7. Massively parallel systems that manage data locality consistent with the time-space dynamics of the application (e.g. Cellular Wave Computing)

Breakthroughs using these thrusts are being sought that will enable 100x-1000x improvements in computational efficiency and are based upon new beyond-CMOS manufacturing technology that can provide a scaling path in the future.



If you liked this article, please give it a quick review on ycombinator or StumbleUpon. Thanks
blog comments powered by Disqus