Images of representative devices. a. Low resolution TEM image of the central SiNx membrane part of a nanowire-nanopore chip. Scale bar = 20 μm. The central bright rectangle is the suspended SiNx membrane area with nanowire-nanopore FETs. Dark lines on the membrane are metal contacts. Yellow arrows point to the source and drain contact of a nanowire-nanopore FET (not visible in gap between two contacts). b. Optical image of the device side of the SiNx membrane chip. Image size = 1.6 mm × 1.6 mm. The central bright rectangle is the suspended SiNx membrane and bright stripes are metal lines connecting FET to the large metal wirebonding pads visible on the edges of this image. c. Photograph of a home-made PCB chip carrier with a SiNx membrane chip glued on. PCB board size = 4 cm × 4 cm. The central dark part is the SiNx membrane chip. Bright metal lines on the chip carrier are copper, which are used to interface the devices to outside instrumentation. A few wire bonding wires are visible between the chip and copper lines. d. Photograph of a PCB chip carrier with assembled PDMS chambers.
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