The goal of 75 GFLOPS/watt would enable a 15 megawatt supercomputer to achieve an EXAFlop of processing.
In the past, computing systems could rely on increasing computing performance with each processor generation. Following Moore’s Law, each generation brought with it double the number of transistors. And according to Dennard’s Scaling, clock speed could increase 40 percent each generation without increasing power density. This allowed increased performance without the penalty of increased power.
As transistor operating voltages approach logic threshold voltage, device operating characteristics change dramatically, decreasing both reliability and maximum operating frequency. Since reliability and operating frequency are critical to its user base, commercial industry has only limited ability to reduce operating voltage to avoid these clock frequency decreases. PERFECT seeks revolutionary approaches to processing-power efficiency to overcome these limitations. This approach includes near threshold voltage operation and massive heterogeneous processing concurrency, combined with techniques to effectively use the resulting concurrency and tolerate the resulting increased rate of soft errors.
PERFECT aims to achieve the 75 GFLOPS/w goal by taking novel approaches to processing power efficiency. These approaches include near threshold voltage operation and massive heterogeneous processing concurrency, combined with techniques to effectively use the resulting concurrency and tolerate the resulting increased rate of soft errors. The program seeks to leverage and incorporate anticipated industry fabrication geometry advances to 7 nanometers. PERFECT does not plan to build hardware, rather it seeks to develop a simulation capability to measure and demonstrate progress. It plans to specifically address embedded systems processing power efficiencies and performance, and is not concerned with developments that focus on exascale processing issues.
PERFECT program envisions three phases. The first phase initiates concept development and looks to provide sufficient proof of impact on processing power efficiency to justify continuing development. The second phase will work to develop technology and techniques to obtain processing system improvement of 75-times greater processing power efficiency. In this phase the performance impact of each development expects to be validated by simulation or equivalent demonstration. The goal of the third phase is to develop each technology or technique and provide a path to implementation.
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