Compared with the traditional forced air convection cooling method which can achieve 50 W cm−2 cooling capability, the CNT microfin on-chip cooling scheme has demonstrated the ability to handle a heat flux as high as 7000 W cm−2, and this can be even higher with thicker CNT microfins and higher water velocity. In contrast to previous research results using other materials as microchannel cooling fins, the structure demonstrated in this study has a power density factor which is two orders of magnitude higher (~320 cm−2 versus ~1–4 cm−2) while still dissipating much higher heat flux on the chip.
Heat dissipation is one of the factors limiting the continuous miniaturization of electronics. In the study presented in this paper, we designed an ultra-thin heat sink using carbon nanotubes (CNTs) as micro cooling fins attached directly onto a chip. A metal-enhanced CNT transfer technique was utilized to improve the interface between the CNTs and the chip surface by minimizing the thermal contact resistance and promoting the mechanical strength of the microfins. In order to optimize the geometrical design of the CNT microfin structure, multi-scale modeling was performed. A molecular dynamics simulation (MDS) was carried out to investigate the interaction between water and CNTs at the nanoscale and a finite element method (FEM) modeling was executed to analyze the fluid field and temperature distribution at the macroscale. Experimental results show that water is much more efficient than air as a cooling medium due to its three orders-of-magnitude higher heat capacity. For a hotspot with a high power density of 5000 W cm−2, the CNT microfins can cool down its temperature by more than 40°C. The large heat dissipation capacity could make this cooling solution meet the thermal management requirement of the hottest electronic systems up to date.
Design and fabrication process of the interface-enhanced CNT microfin on-chip cooling system. (a) Clean Si wafer with SiO2 layer. (b) Fabrication of heating elements and temperature sensors on test chips. Temperature sensors are calibrated by standard RTD. (c) Evaporation of Ti/Au/In for CNT–substrate interface enhancement. (d) Patterning of Al2O3/Fe catalyst layer (10/1 nm thick) for CNT growth on Si substrate by standard photolithography and lift-off processes. (e) Growth of CNT microfins by TCVD using acetylene as carbon precursor. (f) Metal-enhanced CNT transfer onto the test chip surface acting as on-chip cooling microfins. Contact resistance is reduced and adhesion between CNTs and substrate is improved due to the metal enhancing layer. (g) A plastic cover is assembled onto the test chip to form microchannels. The cover is transparent so that the CNT microfins and coolant flow in the microchannels are visible. (h) CNT cooling fin integrated test chip soldered onto supporting substrate. (i) 3D structure in (h). (j), (k) Coolant flow path assembled onto the test chip using adhesive. (l) The test chip with on-chip CNT cooling fins packaged by PDMS for mechanical protection.
We have demonstrated the application of interface-enhanced CNTs as on-chip cooling fins in a microchannel heat sink. Although the cooling performance becomes more and more stable after the thermal conductivity of the cooling fins is higher than 100 W m−1 K−1, the extremely large heat exchange area in the CNT microfins makes the heat dissipation very efficient so that the on-chip cooling structure can handle a heat flux at 1000 W cm−2 scale with the assistance of water. Benefiting from the metal-enhanced CNT interface, the excellent thermal performance and the huge surface/volume ratio of CNTs, this water-assisted CNT microfin on-chip cooling solution exhibits a great capability of cooling down very high power density electric components, and is possible to meet the requirement for managing the thermal budget of the hottest electronic systems to date.
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