In order to fabricate these devices, undoped silicon nanowires with <112> orientations were grown with an catalyst using the VLS method as described in Ref. 4. After etching the Au catalyst, the nanowires were dispersed in VLSI grade isopropanol by ultrasonic agitation and deposited on a 200 nm thick SiO2 layer residing on a p-Si substrate. Thermal oxidation at 875 °C took place to provide a surrounding SiO2 gate dielectric of approximately 10 nm thickness followed by forming gas anneal at 500 °C to passivate interface traps. The Ni reservoirs and source / drain connectors were patterned by electron-beam lithography. Thereby, the SiO2 nanowire shell was etched locally prior to Ni deposition. Upon annealing at 500 °C Ni diffuses axially into the nanowire within the SiO2 shell and transforms into metallic and single-crystalline NiSi2 as described in Ref. 5. Despite the presence of the oxide shell, the silicide intrudes axially into the nanowire. As a result, NiSi2 / intrinsic-Si / NiSi2 nanowire axial heterostructures surrounded by a SiO2 shell are formed. The location of the Schottky junctions is measured by scanning electron microscopy (SEM). Subsequently, individual metal top gate electrodes are patterned overlapping the Schottky junctions.
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