European research institute IMEC has reported a Resistive RAM (RRAM) memory cell that measures 10-nm by 10-nm at the International Electron Devices Meeting, which took place Dec. 5 to 7 in Washington DC. The organization claims this is the smallest such cell and that it shows the potential to replace NAND flash memory.[note 15-nm NAND was revealed at IEDM and it is discussed in the next item below].
RRAM is one of a number of emerging non-volatile memory technologies being researched as a potential replacement for NAND flash, which is based on charge-storage and which in its present form is thought will not scale below about 18-nm planar dimensions
2. EETimes - IEDM: Hynix takes NAND to 15-nanometers
While many experts have expressed doubts about the ability of flash memory to scale and indicated the need for an alternative non-volatile memory technology, Hynix has just gone ahead and produced a 15-nm NAND flash memory cell which it plans to unveil at this year's International Electron Devices Meeting (IEDM).
Hynix also reported on an 84-nm pitch memory process for the production of 1-Gbit phase-change memories and beyond. As memory process are usually denoted by the half-pitch that is effectively a 42-nm process.
Paper 3.3 is Highly Productive PCRAM Technology Platform and Full-Chip Operation Based on 4F2 (84-nm pitch) Cell Scheme for 1 Gb and Beyond, S. Lee et al, Hynix Semiconductor.
Paper 9.1 is A Middle-1X-nm NAND Flash Memory Cell (M1X-NAND) with Highly Manufacturable Integration Technologies, J. Hwang et al., Hynix Semiconductor.
3. EE Times- Sematech researchers will report on high mobility channel materials, improved high-k metal gate reliability advancements, advanced non-planar device doping approaches, and resistive RAM (RRAM) memory technologies for scaled CMOS and memory beyond the 15nm node.
In one paper they will demonstrate a new, conformal, damage-free monolayer doping technique for 20nm FinFETs which is a promising candidate to address key FinFET scaling issues such as series resistance and short channel control for the 15nm node and beyond.
Another paper will examine a novel physical model of RRAM devices that describes the creation of conductive filaments during forming and electrical transport in high- and low-resistance states.
A third paper will identify, for the first time, key factors impacting stress-induced leakage current (SILC) through a comprehensive reliability study of high-k/ metal gate nMOSFETs, including several process changes that promise to mitigate SILC. The researchers will propose an approach to reducing SILC, thereby improving device lifetime.
A fourth paper will analyze BeO films epitaxially grown on Si and GaAs substrates using a conventional atomic layer deposition (ALD) technique.
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