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December 04, 2011

Hybrid Memory cube with 3D memory and 10 times the data speed should be commerially available in 2 years

The Hybrid Memory Cube consortium formed by Samsung Electronics and Micron Technology this October is leveraging IBM Microelectronics' 3D wafer-baking expertise to get HMC memory to market in two years.

IBM said on Thursday (IBM press release) that it has come up with manufacturing breakthroughs to create the conduits that link stacked blocks of DRAM, which IBM Fellow Subu Iyer will present in a paper on December 5 at the IEEE International Electron Devices Meeting in Washington, DC.

HMC will enable a new generation of performance in applications ranging from large-scale networking and high-performance computing, to industrial automation and, eventually, consumer products.

"This is a milestone in the industry move to 3D semiconductor manufacturing," said Subu Iyer, IBM Fellow. "The manufacturing process we are rolling out will have applications beyond memory, enabling other industry segments as well. In the next few years, 3D chip technology will make its way into consumer products, and we can expect to see drastic improvements in battery life and functionality of devices."

"HMC is a game changer, finally giving architects a flexible memory solution that scales bandwidth while addressing power efficiency," said Robert Feurle, Vice President of DRAM Marketing for Micron. "Through collaboration with IBM, Micron will provide the industry's most capable memory offering."

The breakthrough is significant enough for Micron to license IBM's wafer-baking techniques and to commission Big Blue to manufacture some of the necessary logic circuits in an HMC memory module.




The TSVs (Through Silicon Vias) that IBM is laying down in its manufacturing technique are copper, and integrate nicely with the high-k metal gate processes that Big Blue uses to make the embedded DRAM on its Power7 and System z10 processors. The technique can obviously be applied to standard DRAM – and in fact, Micron is using IBM's technique to make the TSV interconnects that will lash together its own DRAM chips.

The HMC logic circuits underpinning the cubes will be made using IBM's 32-nanometer high-k metal gate process from its East Fishkill, New York fab. These logic circuits will be shipped off to one of Micron's 300mm fabs in Boise, Idaho, where they will be mated with stacked memory modules and their TSV pipelines etched by Micron.

By stacking the DRAM chips in a 3D cube, the real estate in a server or PC can be significantly reduced or the memory capacity or bandwidth can be significantly increased – we all vote for the latter, of course. IBM and Micron say that HMC devices can take up about a tenth the space of traditional 2D DRAM memory sticks and require 70 per cent less energy to transfer a bit of data from the memory chip to the CPU.

The best part is that the HMC prototype modules that have been manufactured to date can deliver around 128GB/sec of bandwidth into and out of the memory block using DDR3 memory chips, compared to 12.8GB/sec for 1.33GHz DDR3 memory sticks made in a conventional 2D layout.

The HMC consortium, which includes Altera, Open Silicon, Xilinx, and now IBM, has gotten some love from Intel recently, as well, but it seems unlikely that Intel will re-enter the memory market is exited decades ago.


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