European scalable and power efficient HPC platform based on low-power embedded technology (12 pages)
Objective 1: To deploy a prototype HPC system based on currently available energy-efficient embedded technology
•Scalable to 50 PFLOPS on 7 MWatt
•Competitive with Green500 leaders in 2014
•Deploy a full HPC system software stack
This will need
•7 GFLOPS / Watt efficiency
•Required improvement on energy efficiency
•3.5x over Blue Gene/Q
• 5x over ATI GPU systems
• 7x over Nvidia GPU systems
•8.5x over SPARC64 multi-core
• 9x over Cell systems
Rack:
32x Board container
10x 48-port 1GbE switches
256x Q7 carrier boards
256x Tegra3 SoC
1024x ARM Corext-A9 Cores
256x GT520MX GPU
1TB DDR3 DRAM
38 TFLOPS
~5 Kwatt
7.5 GFLOPS / W
Objective 2: To design a next-generation HPC system and new embedded technologies targeting HPC systems that would overcome most of the limitations encountered in the prototype system
•Scalable to 200 PFLOPS on 10 MWatt
•Competitive with Top500 leaders in 2017
•Objective 3: To port and optimise a small number of representative exascale applications capable of exploiting this new generation of HPC systems
•Up to 11 full-scale applications
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