August 19, 2011

Tensilica DSP core does 100 GMACs at 1W

EETimes - Tensilica described a new integer DSP core for next-generation cellular applications that when made in a 28nm process can compute 100 GMACs/second at less than a Watt. The BBE64 core is a new instruction set architecture based on the companies' current Xtensa LX4 core.

The BBE64 combines SIMD and VLIW concepts and lets designers configure processors for a range of handset and base stations uses. Rowen said the core run at data rates of "a few hundred MHz" could process 2x2 MIMO LTE Advanced signals at 1 Gbit/second across 100 MHz of spectrum.



Texas Instruments ships chips using an array of eight DSP cores that computes 320 GMACs/second and 160 GFlops. TI uses a single core that handles both integer and floating point math.

Using separate integer and floating point cores would cost extra die area and power, one TI engineer said. Integer math lacks the accuracy of floating point calculations and would require programmers to make complex conversions, he said.

Tensilica is playing catch up with DSP core designer Ceva in the burgeoning cellular sector. Ceva commands as much as 90 percent of the business for licensed DSP cores in cellphone baseband processors, according to Will Strauss, principal of Forward Concepts. Ceva became the largest cellular baseband provider last fall, surpassing Qualcomm and others.

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