There was a conference set up by the Dept of Energy to look at the technical issues for building Exaflop supercomputers and beyond.
Presenter Presentation Title
Agarwal, Anant The Road to Exascale: Are We Being Radical Enough?
Bergman, Keren Silicon Photonics for Exascale Computing
Borkar, Shekhar Technology and Design Challenges to Realize Exascale
Dally, Bill Power and Programmability The Challenges of ExaScale Computing
Elnozahy, Mootaz Lessons from HPCS/PERCS
Geist, Al The Path to Exascale What is the Monster in the Closet?
Jouppi, Norman Research Gaps in Photonics, Memristive Memories, and Architecture
Kogge, Peter Update on Current Trends and Roadblocks
Mountain, David An ACS view of the current Exascale efforts
Murphy, Richard Through the Exascale Looking-Glass and What Alice Found There
Resnick, Dave Needs Within and Above the Exascale Program
Resnick, Dave Memory for Exascale and ... Micron's new memory component is called HMC: Hybrid Memory Cube
Shalf, John Exascale: Past, Present, Future
Snavely, Allan Whose job is it to find locality?
Sterling, Thomas Exascale Execution Models
Micron Hybrid Memory Cube
Micron Hybrid Memory Cube uses TSVs (Through Silicon Vias) to interconnect multiple memory die on a CMOS chip base.
* 1 HMC has ~20 times the performance of a DDR3 DIMM (8 to 72 memory parts)
* 1 HMC uses ~10% of the energy per bit compared to current DIMMs and memory channels
Future HPC Technology Building Blocks
– Optimization target: minimize price to buy more hardware
– COTS: Redirect off-the-shelf components designed for mass market
– This leveraged “Moore’s Law” density improvements
• Next Decade
– Optimization target: minimize power consumed for work performed
– Specialize and integrate: Embedded + SoCis proven design point
– This leverages “Bells Law” cost efficiency: Commodity not COTS
FPGAs were used to find opportunities to speed up a job by making things more local.
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