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November 29, 2010

A*STAR Institute Of Microelectronics and Stanford University to Co-Develop Nanoelectromechanical Relay Technology for Ultra-Low Power Applications

The Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR), today announced a collaborative partnership with Stanford University in USA to develop nanoelectromechanical (NEM) relay technology to enable ultra-low power computation. NEMS-based integrated circuits are ideal for a wide range of emerging green electronics solutions as they eliminate leakage power, one of the leading sources of power consumption in today’s scaled devices.

The project will be jointly led by Dr Navab Singh, Principal Investigator of the Nano-Electronics Programme at IME, and Professor H.S. Philip Wong, Professor Roger Howe, and Professor Subhasish Mitra from Stanford University.

“Not only do the NEMS devices allow much greater integration density to enable even smaller form factor to be attained, these devices are also suitable for use in robust electronic systems, given their high tolerance to harsh operating environments,” said Dr Singh. “This project extends and strengthens our R and D partnership with Stanford University.”

Some nanomechanical relay research at Stanford from earlier in 2010 -
Titanium nitride sidewall stringer process for lateral nanoelectromechanical relays

This paper reports on lateral nanoelectromechanical (NEM) relays based on variations of a two- or three-mask titanium nitride (TiN) sidewall stringer process. Electrically isolated TiN perimeter beams are fabricated from stringers formed on the inside walls of polysilicon trenches, yielding 200 nm wide TiN fins and 200 nm gaps; these dimensions are 3X smaller than the resolution limit of the optical lithography tool (600 nm) utilized. The reduction in the operating voltage is about a factor of 5 compared to 600 nm wide polysilicon beams. Simple scaling could potentially enable sub-1V operation. Five-terminal NEM relays demonstrate successful switching in both directions over 1000 DC-sweep cycles with low drain bias (100 mV).



Stanford NEMS logic and memory research

On the joint partnership, Professor Wong said, “Our collaboration will leverage on IME’s established CMOS platform and state-of-the-art clean room infrastructure to develop a practical and robust process flow for NEMS device fabrication. The success of a CMOS-compatible process flow will drive down the production costs of these state-of-the-art NEMS devices to accelerate other emerging applications in electronics, chemistry and biology, not just ultra-low power computation.”

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