Cray is building more support for accelerators (like GPGPUs) for regular Intel/AMD chips for their supercomputers.
Further down the road, heterogeneous processing will form the foundation of Cray exascale architectures. In 2018, the year Scott predicts Cray will have a machine that can deliver a sustained application exaflop, heterogeneous computing will likely be much more highly integrated. According to Scott, CPU-GPU hybrid processors (or the equivalent), along the lines of AMD's Fusion architecture, will be generally available and powerful enough to form the basis of HPC machines. He believes both NVIDIA and Intel will be offering their own versions of integrated CPU-accelerator chips. "That's clearly the direction to take," he asserted. "The more tightly you can couple those two different types of processors together, the better off we'll be."
Cray recently announced their XE6 Baker Supercomputer.
Cascade Supercomputer on Track for 2012
The development of Cascade is being subsidized by DARPA's HPCS (High Productivity Computing Systems) program. The third and final phase of the contract with Cray set aside $250 million to help the company complete development of the hardware and the supporting system software. (IBM was allocated $244 million for its corresponding PERCS system.) According to Scott, Cascade is currently on track to be delivered sometime in the second half of 2012. Specific product timetables for the Opteron version are still to be determined, and will ultimately depend upon customer demand as well as AMD's processor schedule.
A new system interconnect, codenamed "Aries," is being developed for the Cascade-class machines. To support a dual Intel-AMD strategy on this architecture, Cray is going to begin using PCI-Express as the processor interface to the interconnect ASIC. The current SeaStar, and now Gemini interconnect, are tied to Opteron's native HyperTransport link. While it might seem natural to think that Cray would hook into Intel's QPI for network connectivity on a Xeon-based machine, opting for PCI-Express meant Cray could support the same network across both processor architectures -- and any future ones as well. According to Scott, they're looking to tape out the Aries chip by the end of 2010.
For Cray, Cascade represents a fairly significant break with the XT/XE line of supercomputers, which have maintained a smooth hardware upgrade path for the past six years. Although the software stack and application codes can be carried forward onto Cascade, the reworked hardware architecture means users will no longer be able to extend their XT or XE infrastructure with this new technology. Cascade will also have an accelerator blade to go along with the x86-based blades.
Beyond the exascale, Cray has nothing on the drawing board yet, but neither does anyone else. Assuming, historical trends hold, the first zettaflop systems will show up around 2028. But they are likely to be based on technologies that have yet to make it out of the research lab
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