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March 13, 2010

IBM Work on 3D chip stacking will take Moore's Law to 2025

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Last week, IBM, École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH) signed a four-year collaborative project called CMOSAIC to understand how the latest chip cooling techniques can support a 3D chip architecture.

Unlike current processors, the CMOSAIC project considers a 3D stack-architecture of multiple cores with a interconnect density from 100 to 10,000 connections per millimeter square. Researchers believe that these tiny connections and the use of hair-thin, liquid cooling microchannels measuring only 50 microns in diameter between the active chips are the missing links to achieving high-performance computing with future 3D chip stacks.

The CMOSAIC project description

The CMOSAIC project is a genuine opportunity to contribute to the realization of arguably the most complicated system that mankind has ever assembled: a 3D stack of computer chips with a functionality per unit volume that nearly parallels the functional density of a human brain. CMOSAIC's aggressive goal is to provide the necessarily 3D integrated cooling system that is the key to compressing almost 10^12 nanometer sized functional units (1 Tera) into one cubic centimeter with a 10 to 100 fold higher connectivity than otherwise possible. Even the most advanced air-cooling methods are inadequate for high performance 3D-IC systems where the main challenge is to remove the heat produced by multiple stacked dies in a 1-3 cm3 volume, each layer dissipating 100-150 W/cm2.


Aquasar Ten Teraflop Supercomputer



Aquasar press release

To solve the cooling challenge, the team is leveraging the experience of IBM and ETH in the development of Aquasar, a first-of-a-kind, water-cooled supercomputer. Similar to Aquasar, the team plans to design microchannels with single-phase liquid and two-phase cooling systems using nano-surfaces that pipe coolants—including water and environmentally-friendly refrigerants—within a few millimeters of the chip to absorb the heat, like a sponge, and draw it away. Once the liquid leaves the circuit in the form of steam, a condenser returns it to a liquid state, where it is then pumped back into the processor, thus completing the cycle.

"As we will demonstrate with ETH in the Aquasar project, employing microchannels carrying liquid coolants offers a significant advantage in addressing heat-removal challenges, and this should lead to practical 3D systems," said Bruno Michel, manager advanced thermal packaging, IBM Research - Zurich. "Water as a coolant has the ability to capture heat about 4,000 times more efficiently than air, and its heat-transporting properties are also far superior." Chip-level cooling with a water temperature of approximately 60°C is sufficient to keep the chip at operating temperatures well below the maximally allowed 85°C. The high input temperature of the coolant results in an even higher-grade heat as output, which in this case will be about 65°C.



Aquasar--the new supercomputer, which will be located at the ETH Zurich and is planned to start operation in 2010, will reduce overall energy consumption by 40%. The system is based on long-term joint research collaboration of ETH and IBM scientists in the field of chip-level water-cooling, as well as on a concept for "water-cooled data centers with direct energy re-use" advanced by scientists at IBM's Zurich Lab.

The water-cooled supercomputer will consist of two IBM BladeCenter® servers in one rack and will have a peak performance of about 10 Teraflops


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