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March 06, 2010

Europe Targets Nanoscale Computer Memory with 16 nanometer and Eventually 5 nanometer Features

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There is a European project to design nanoscale memory for the computers of the future. The Terascale Reliable Adaptive Memory Systems (TRAMS) initiative is a Future Emerging Technologies (FET) collaborative research project approved by the European Commission as part of the Seventh Framework Program for Research and Technological Development.

The starting point will be the latest Complementary Metal Oxide Semiconductor (CMOS) technologies, which are the most commonly used in the manufacture of integrated circuits in most electronic products. The project includes the study of the new generations of chips with transistor sizes below 16 nm (whereas the current ones are 32 nm), as well as architectures with advanced devices (multigate devices, which are controlled from two or more different electrodes). It will also study new gate and channel materials that are being designed with a scale of less than 10 nm (they can be as small as 6 nm).

In addition, the project will also analyze emerging technologies, such as nanowire transistors, quantum devices, carbon nanotubes, graphene and molecular electronics, which are expected to reach sizes of less than 5 nm.

All of this new technology promises an increase in the density of integration of components, as well as performance and functionality, to hundreds of times the current values. However, at this scale, a dramatic reduction in the quality and reliability of components is also expected, with intense degradation effects, a sharp reduction in the signal to noise ratio and extreme variability of characteristics. Thus it is necessary to research new techniques and design rules for circuits and systems to guarantee reliable and robust systems in spite of the reduced quality of the components. To enable reliable, robust, fault and defect tolerant nanoscale memory systems to be built at a reasonable cost and with less designer effort, the TRAMS project will study these new devices, define new design paradigms and implement principles of hierarchical design.

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