February 15, 2010

Toshiba and AIST Improve Lithography Masks to 6 Nanometer Accuracy

Toshiba Corporation (TOKYO: 6502) and the National Institute of Advanced Industrial Science and Technology (AIST) today announced joint development of a mask pattern optimizing technology that improves the accuracy of lithography for LSIs by approximately 20%. The technology opens the door to extending the life of current ArF immersion lithography to the next generation and beyond.

In mask patterning, the accuracy of the resolution and critical dimensions (CD) of the main circuit patterns are enhanced by application of a sub pattern, the Sub Resolution Assist Feature (SRAF), which modulates printed images of the main pattern. Optimization of SRAF placement is becoming increasingly difficult as lithographic exposure approaches its resolution limits. The new technology applies an adaptive search algorithm based on the optimal gradient method to optimize the placement of SRAF which improves positioning and CD accuracy by approximately 20%.

In order to overcome those weaknesses, Toshiba and AIST developed an adaptive search algorithm based on the optimal gradient method, in order to secure optimal SRAF placement. The new search algorithm carries out a local search, repeatedly seeking the best solution nearest to the current one, towards efficient achievement of an optimum solution. Application of the method enhances CD accuracy to 6nm, a 20% improvement. Used in combination with the interference map method the new technology achieves higher accuracy and higher efficiency than other methods.

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