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February 08, 2010

ISSCC - Silicon Could Scale to 7.9 nanometers, Graphene Favorite for Post-CMOS and Call to Increase Energy Efficiency 100 Times

EETimes reports from International Solid State Circuit Conference (ISSCC)

For processors, silicon could scale to the 7.9-nm node, which is slated for 2024.

Reasons Graphene is the post-CMOS Favorite by James Meindl, director of the Joseph M. Pettit Microelectronics Research Center :

1. Graphene has a mechanical strength-to-weight ratio exceeding that of any known material.
2. Carrier mobility exceeds 200,000-cm2/Vs.
3. Carriers with zero effective mass that propagate as 'Dirac fermions' in a manner similar to photons with a velocity 300 times less than the speed of light without scattering for distances in the micrometer range.
4. The capacity to conduct current densities as large as one thousand times greater than copper without electromigration.
5. Record values of more than 5,000W/mK for room temperature thermal conductivity.
6. The capability to serve as a source, channel drain regions of a field effect transistor (FET) and as an interconnect.


EETimes also reports that power efficiency is the single biggest challenge facing the mobile handset industry, and collaboration is needed to enable the industry to deliver a required 100X improvement in power efficiency for mobile devices, according to a keynote presentation at the International Solid State Circuits Conference.

Greg Delagi, senior vice president of wireless at Texas Instruments Inc., said the future vision of always on, always connected mobile computing depends heavily on engineers' ability to improve power efficiency through techniques such as ultra-low voltage and power circuits, high-efficiency DC-DC and DAC converters, SRAM, non-volatile memory and parallel architectures. He outlined promising research in areas such as ultra-low power video codecs, DC-DC converters, medical processors and energy scavenging—the ability to generate power from the surrounding environment—which he called the "holy grail."

While many would agree with Delgai's assertion that power efficiency is the single biggest issue facing mobile devices, the 100X improvement he said is required is likely to generate attention. Still, he said TI reduced the leakage power of its OMAP-3 processor by 300X at the 65-nm node and that its OMAP-4 processor offered 1,000X reduction in active power on top of that. He credited multiple technologies, incluindg SRAM and logic retention, channel length, dynamic voltage and frequency scaling and others.




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