Four different kinds of double lithography. Click on the image for larger view
Double patterning is a class of technologies developed for photolithography to enhance the feature density of computer chips. The resolution of a photoresist pattern begins to blur at around 45 nm half-pitch. Double patterning is the only lithography technique to be used for the 32 nm and 22 nm half-pitch nodes in 2008-2009 and 2011-2012, respectively, using tools already available today.
State-of-the-art 193 nm tool with a numerical aperture of 1.35 can extend its resolution to 18 nm half-pitch with double patterning. Even electron beam lithography may eventually require double patterning (due to secondary electron scattering) to achieve comparable half-pitch resolution, for instance, in the fabrication of 15 nm half-pitch X-ray zone plates. Due to this ability to use coarse patterns to define finer patterns, it offers an immediate opportunity to achieve resolution below 30 nm without the need to address the technical challenges of expensive next-generation lithography technologies such as EUV. Brion Technologies has targeted the double patterning software market down to 22 nm. Hynix has already endorsed Brion's Tachyon DPT software as a key part of the double patterning solution
Double exposure is a sequence of two separate exposures of the same photoresist layer using two different photomasks. As long as double exposure can be used effectively and is kept within alignment tolerances, it is the preferred patterning approach since it does not require additional follow-up process steps.
A spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled.
Double Expose, Double Etch (mesas)
A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample. This second layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is therefore a set of photoresist features in between hardmask features, which can be transferred into the final layer underneath. This allows a doubling of feature density.
Double Expose, Double Etch (trenches)
A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns.
Triple and Quadruple Patterning
Compared to single patterning, double/triple/quadruple patterning increases processing steps (coating, lithography, etching) by a factor of 2/3/4 for linear (1D) pattern layers. For 2D arrays, direct exposure would lead to a squaring of this increase (4/9/16 respectively) for fabricating a single layer, but self-aligned processing would only lead to doubling (4/6/8 respectively) for fabricating two separate layers. If the diagonal design rule is lithographically allowed, the 4 exposures required for 2D double patterning could be halved to 2.
Synopsys has begun consideration of triple patterning decomposition of layers which are less easy to split into two patterns, such as contact layers. While only increasing the number of processing steps by 50% (compared to 100% for the insertion of double patterning), triple patterning would enable 16 nm node patterning on a 45 nm node lithography tool. Likewise, quadruple patterning would enable 11 nm node patterning on the same 45 nm node lithography tool, with only 33% additional steps over triple patterning.
October 2008 Discussion of the Readiness of Next Generation Lithography (NIL)
Why isn't NIL in production (for ICs)? Throughput is only at 4wph [full scale lithorgraphy is at a speed of about 120 wafers per hour]; overlay is at 15nm (nanometers). Inspection and repair infrastructure is not ready. The risk of repeating defects on the production line also needs to be addressed. How can people monitor for such problems and remove a template for cleaning when a printing defect is observed?
It appears the IC industry will finally adopt EUV for some layers at the 22nm node and for many more layers at the 16nm node.
Outlook for 15 Nanometer CMOS Status (National Device Labs Taiwan)
32 page presentation on the outlook for 15 nanometer CMOS from May 2009.
Some are quite optimistic for 15 nanometer EUV (Extreme Ultra Violet) Lithography for 2012-2014.
E Beam Lithography
E-beam lithography hinges on increasing the throughput with many parallel beams
Nanoimprint is getting more durable with higher resolution.
Materials for 15 nanometers
Risks Getting to 15nm
Nanopatterning market study projects Global Nanopatterning Market to Reach $481.48 million by 2012.
Nanoimprint Lithography (NIL) exhibits the most promising outlook. With anticipation that NIL emerges successful for commercial semiconductor manufacturing at 32nm node in the near future, the market for NIL is projected to grow the fastest between 2008 and 2015. Of the NIL techniques, UV nanoimprint lithography is projected to grow the fastest from 2008 to 2015. Another NIL technique expected to perform exceedingly well is hot embossing lithography.
The second largest nanopatterning market, Scanning Probe Lithography, would see its share decline from 2008 to 2015. Among the diverse applications, semiconductor applications and microelectronics fabrication represent the largest nanopatterning application.