Computational lithography was used at the 32 nanometer lithography node.
Intel technologists have also been working with computational lithography which involves etching pixels with various shapes and slopes on what appears to be a totally transparent, chromeless piece of glass. When 193 nm light is projected, the pixelated mask creates phase-shifted patterns that could extend immersion lithography to 22 nm.
Introducing circuits at 22nm is a challenging milestone since current lithography methods -- the process of designing photomasks to image circuit patterns on silicon wafers in mass quantity -- are not adequate for critical layers at 22nm due to fundamental physical limitations. Computational Scaling overcomes these limitations by using mathematical techniques to modify the shape of the masks and characteristics of the illuminating source at each layer of an integrated circuit.
The individual components of IBM's CS solution include:
Source Mask Optimization
IBM has partnered with Mentor Graphics on a new resolution enhancement technique to enable cost-effective printing of two dimensional patterns for the 22nm semiconductor technology generation. This new technology, know as source mask optimization, will provide a means to minimize the use of double patterning by employing highly customized sources with optimized mask shapes.
"Our partnership with IBM will ensure production-ready technologies are in place when they are needed for the 22nm node," said Joseph Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. "Because this next generation solution will be built on the familiar Calibre platform, designers will see a smooth transition path to 22nm, and will also enjoy added benefits in managing turnaround time and the cost of computing."
Together with Rensselaer Polytechnic Institute and the State of New York, IBM has made significant investments in the area of high performance computing and remains devoted to the advancement of semiconductor technology through the establishment of the Computational Center for Nanotechnology Innovations (CCNI). CCNI provides the unprecedented computational power to enable accurate predictions of advanced manufacturing processes. When combined with predictive models and TCAD, this platform will allow virtual co-optimization of semiconductor unit processes and critical circuit design elements to cut development learning cycles and improve time-to-market for advanced semiconductor technology.
Design Technology Co-Optimization
Within semiconductor fabrication, design 'rules' are created as an abstract representation of the information or model that describes the technology being created. Often, these rules are only defined after an exhaustive negotiation process between the technology and design team. To improve the timeliness and certainty of this process, IBM's Design Technology Co-optimization (DTCO) process helps integrate and automate this complex procedure, cutting the time it takes to reach a clear and stable set of rules for use by the circuit design teams.
Design Enablement Tools
As a result of using IBM's DTCO, a semiconductor modeling process will have a new class of design rules that are simpler and more prescriptive (what to do vs. what not to do). Working with engineering design automation (EDA) suppliers, IBM will be providing new design enablement solutions for a seamless transition.
Critical Dimension Variance Control
Working with leading equipment suppliers, IBM will play the role of lead integrator of providing an adaptive control system to minimize critical dimension variance. As a result production yield and circuit parameters will be more stable reducing the cost of production.
To address the gap in raw optical resolution, aggressive resolution enhancement techniques such as SMO drive unprecedented minimum feature sizes on the photomask -- the opaque plate with holes or transparencies that allow light to shine through in a defined guide for casting the circuit patterns. IBM has partnered with Toppan to ensure timely availability of masks with the required feature sizes.