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July 02, 2008

Intel's Gelsinger sees clear path to 10 nanometer lithography

Intel's Pat Gelsinger (NSDQ:INTC) sees a "clear way" to manufacturing chips under 10 nanometers and when the semiconductor industry transitions to 450mm silicon wafers around 2012, the number of companies that run their own fabs will drop into the single digits.

Intel debuted its 45nm process late last year and has been ramping its Penryn line of 45nm processors steadily throughout this year. The next die shrink milestone will be the 32nm process, set to kick off next year, followed by 14nm a few years after that and then sub-10nm, if all goes according to plan.

Gelsinger described the elemental hoops Intel has had to jump through to achieve each "tick" milestone in the chip maker's relentless pursuit of Moore's Law, noting that while each new process adds materials used in novel ways, modern processors are still built on a "silicon scaffolding."

"We are putting more and more of the periodic table onto that silicon scaffolding. Today we use about half of the elements on the periodic table. When [Intel co-founder Robert] Noyce and Moore started, they used six elements," Gelsinger said.

"We replaced the gate with high-K, we put metal on top of it, but it's still, quote, silicon. [The process of getting smaller] keeps moving forward. It may be carbon nanotubes next or it may be spintronics. But we'll keep moving forward."


ULTIMATE LIMITS
Previously Intel has forecast moore's law to continue to at least 2029.

This site has covered the future of lithography

There is going to be substantial re-architecting with more photonics and other changes like the Tensilica processors.

The GPGPU, FPGA, custom tensilica processors and cell type processors seem like the way forward. Plus the new universal memories.

New molecular computing architectures could have an impact or a niche.

A successful and inexpensive 3D architecture needs to be perfected. Ultimate limits will not be seen until we have 3D, 10 nanometer or less optical systems and are pushing the limits of cooling the heat generated and energy to power the devices. The technologies that could be involved are plasmonics, excitons, spintronics, metamaterials, room temperature superconductors and better cooling systems. There will be re-architecting with reversible computing architecture and more efficient parallel computing architectures.

So a 10 centimeter cube would have 10 million multi-nanometer layers. One layer of computing would be about 10 million times more powerful than what we currently have. so the small fist size cube would be100 trillion to 1000 trillion times more powerful for personal computing. This means 100,000 to 1 million zettaflops (10*23 to 10**24). Plus each person could have a few cubic meters of computronium. For
several more thousand times more compute power.

Heading to 1-2 nanometer feature and component sizes would probably also be possible for another 1000 times boost (The previous insane amount of compute power ought to help find a way to squeeze out another 1000-1 million improvement) (10**27 to 10**30)

For non-heroic cooling limits: 10**24 to 10**26 bits per cm**2 (but we added the third dimension for 10 million to 100 million fold gains)

There will also be comparable levels of scale and density for quantum computers (10**23 to 10**32 qubits)

All the individual compute power will be networked together across the solar system. The connection speeds will also be pushing whatever physical limits there are.

FURTHER READING
Intel is researching applications for this compute power

30 page transcript from the IDF (Intel Developers Forum) spring 2008 keynote address by Pat Gelsinger

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