Pat Gelsinger, head of the Digital Enterprise Division at Intel, says that Moore's Law will continue until 2029 with zettaflop supercomputers at that time. [link is to his Intel Developers Forum keynote address, 80 pages, From Petaflops to Milliwatts]
Pat expects by 2017 it will be possible to create a complete genetic simulation of a cell, which would require an exaflop (10 to the 18th power floating-point operations) per second.
I have covered Tensilica's configurable processors which could be one of several approaches to accelerating or at least maintaining Moore's law computer performance progress to exaflops and beyond
From a 38 page study of detailing petaflop and exaflop scale computing challenges
Some have expressed concerns that silicon will stop having performance improvement [from shrinking lithography stalling out] in as little as four years.
The Inquirer also has another quote from Pat Gelsinger on Moore's law from the same event.
"I compare Moore's Law to driving down the road on a foggy night, how far can you see? Does the road stop after 100 metres? How far can you go?
"That's what it's been like with Moore's Law. We thought there were physical limits and we casually speak about going to 10 nanometres. "We have work going on different transistor structures. Silicon has become scaffolding for the rest of the periodic table. We're putting these other structures into the materials. We see no end in sight and we've had 10 years of visibility for the last 30 years.
Intels chips now and future
- Quad-core with 30 MB cache core with 30 MB cache
- 2 billion transistors
- Multi-threading technology threading technology
- Intel QuickPath QuickPath interconnect interconnect
- Dual integrated memory controllers
- Estimate 2 times performance of dual core Itanium 9100 series
- Mainframe-class RAS
Dunnington 6 cores
- 45nm high-k technology
- 1.9B transistors
- 16 MB L3 cache
- Caneland socket compatible socket compatible
- Latest Intel virtualization technologies
Press room for the Intel Spring 2008 developer's forum
Zettaflop architecture challenges
Frontiers of Extreme Computing 2007 workshop was held in Santa Cruz, CA October 21-25, 2007.
Ab initio million-atom electronic structure simulations.
Communication challenge in ultradense computing devices
DARPA MoleApps–Aim: 10**15devices/ cm**3
17 nm half-pitch,3.5*10**11 /cm**2 demonstrated
Communication speed of 80 TB/s for full speed 2017 chips