Next-generation memories--such as FRAM, MRAM, PCM and others--are supposed to replace today's DRAMs and flash memory technologies. Current memory devices are expected to hit the wall, as the floating-gate reaches its physical limits.
Intel Corp. and STMicroelectronics Inc. reached a milestone, as they begin shipping prototype samples of their previously-announced phase change memory (PCM) line. The 90-nm, 128-megabit product is slightly late to the market; the companies were supposed to ship the device late last year.
As RAM and flash technologies run into scaling limitations over the next decade, PCM costs will decline at a faster rate, Intel and ST claimed, further predicting that the advent of multi-level-cell PCM will accelerate the cost per bit crossover of PCM relative to today’s technologies. The duo also projected that by combining the bit-alterability of DRAM, the non-volatility of flash, the fast reads of NOR, and the fast writes of NAND, PCM has the ability to address the entire memory market and be a key driver for future growth over the next decade.
Intel has said that it has produced prototypes of PCM devices and is shipping samples to customers now. Codenamed “Alverstone” the devices are 256 Mb multi-level (2 bit) cell devices manufactured in 90 nm. Taking the prototype down to leading edge lithography levels of 45nm would increase the 2 bit cell technology to 1 Gb, which is still behind the latest flash at 16 Gb.
Unofficially, the 90-nm, 128-Mbit part is being billed as a NOR flash compatible replacement. Cliff Smith, technical industry manager at Intel, said that the part provides fast read and write speeds at lower power than conventional flash, and allows for bit alterability normally seen in RAM.
According to Al Fazio, memory technology development director, Intel, only three memory technologies that more or less meet the next generation memory criteria: MRAM, FeRAM and PCM, with the latter being the most promising. PCM is the most promising because it appears to have the capability to scale down to 5 nm and beyond.
PCM is already proven in certain applications; it is the material that is used in rewritable CD-ROMs. There, it is used with a laser — photon energy changes its material from an amorphous to a crystalline state. “We’re trying to use an electrical current — IR heating — instead of light to change the memory,” Fazio said. “While it’s doable, it hasn’t been proven on a large manufacturing base. That’s a major hurdle — moving this feasibility, the basic capability, to the manufacturing floor.” Another PCM concern is that although there are many studies showing that it is scalable down to probably <5 nm dimensions, producing a device around it is a different matter. “How do you build the device structure, what’s the wordline/bit line configuration of that array, how do you get all of this to work in those small dimensions? I have little doubt that it will be solvable, but it will require work,” Fazio said.
Meanwhile, in recent times, Freescale, NEC and others have rolled out rival MRAM devices. And Texas Instruments and others claim to be shipping another competitive technology called FRAM.
Japan's NEC recently claimed that it has developed the world's fastest MRAM. NEC's new ''SRAM-compatible, MRAM'' can operate at 250-MHz. The MRAM has a memory capacity of 1-megabit.
The MRAM is still in the development stages, and eventually, it will be targeted for select markets, said Masao Fukuma, senior vice president of NEC Electronics Corp. "Embedded memory is our first target," he told EE Times at ISSCC
SanDisk builds NAND flash chips with 3-bit cells when others had only offered 2 bit cells
Several firms are working on NAND flash structures with 4-level cells. SanDisk is using the intermediate step x3 MLC with three bits per cell, developed jointly with its partner Toshiba, for a 16-gigabit chip.
In comparison with single-level cell (SLC) NAND flashes, which are more expensive because of their larger die areas, MLC memory chips do, however, have disadvantages. The number of write cycles that each individual cell survives is typically around 10,000 for MLCs, but the figure for SLCs is usually 100,000. Error correction for MLCs requires a more expensive 4-bit ECC technique, whereas 2-bit ECC is sufficient for SLCs. The higher cost of signal processing, moreover, reduces the data-transfer rate.
A closely related chip with x2 MLC and half the capacity, on the other hand, is to achieve more than 60 Mbytes per second. SanDisk quotes only 8 megabytes per second for writing to the x3 MLC NAND flash. SLC NAND flashes are therefore still commonly built into fast solid-state discs (SSDs). Intel and Micron had also announced ONFI 2.0 NAND flashes with a capacity of eight gigabits and a write-data transfer rate of up to 100 Mbyte/s at ISSCC 2008.
SanDisk intends to begin shipping products. Shipments will start with 16-Gbit devices, followed by 32-Gbit parts in the second half of 2008.
Another alternative memory is programmable metallization cell or nanoionic memory