On the chip, next to certain ubiquitous circuits called flip-flops, they placed similar circuits called latches. Though both the flip-flops and the latches had the same input, the data reached the latches a quarter or a half cycle later. Data is supposed to come into the flip-flop at a particular phase of the clock signal, but if there’s an error, it comes in late and the latch catches it instead. If the bits measured by the flip-flop and the latch don’t match, a controller knows there was an error and tells the processor to rerun whatever instruction was affected.
Of course it takes time to detect the error and rerun the instruction. But that minor drop in performance is more than compensated for by the performance gained when all the error-free circuits do their work so much faster. Blaauw says in his setup, which is known as Razor II and is a simplified version of a similar scheme he presented three years ago, detecting and correcting errors costs about 2.5 percent of the chip’s total power consumption. But by using Razor II, he can run it at so much lower a voltage that he’s putting 35 percent less power into the chip overall and getting the same performance. Intel, on the other hand, kept the power consumption the same and reported a gain in performance of between 25 percent and 32 percent. “We work hard for a few percentage points of improvement, so getting this much is a lot,” Mooney says.
It could take about three years to develop the setup for commercial use, although Mooney says that Intel has no plans for a product based on the technology at the moment. Intel researchers are trying to implement the technology using fewer, smaller transistors and reducing the clock power to make the whole thing more efficient.